This invention relates to a method of manufacturing a semiconductor device involving the step of impurity ion implantation. When a semiconductor device is manufactured, the well-known process is one which involves the step of implanting impurity ions in a substrate to fabricate a layer of a prescribed conductivity type. In the case of, for example, a GaAs integrated circuit, an active layer is produced in a semiconductor substrate by ion implantation to provide source and drain regions of high impurity concentration. Due to the high integration and increased speed of operation of semiconductor devices, greater demand is made for the precise control of ion implantation.
When a layer of a prescribed conductivity type is formed by ion implantation, it sometimes happens that a channeling phenomenon appears, in which an impurity ion is implanted to a greater depth in a particular direction of implantation depending on the structure of a single crystal substrate. With a semiconductor single crystal substrate whose surface parallel to the (100) plane, it is known that when the implantation of an impurity is carried out perpendicularly to the substrate, an axial channeling takes place because crystal lattices are widely separated from each other. The phenomenon of channeling becomes more noticeable as the constituent atoms of the substrate, and ions to be implanted have a larger atomic number, and the acceleration voltage for ion implantation decreases. When, therefore, an activated layer is made thinner for higher integration, the channeling more readily takes place. The conventional practice to avoid such a drawback is to incline the main substrate plane by some degrees to the ion implantation direction in order to avoid axial channeling, and further, to rotate the substrate about the surface normal axis several or scores of degrees, thereby avoiding plane channeling.
The conventional method of manufacturing semiconductor devices mentioned before is also accompanied with the following drawbacks. Since ion beams enter obliquely into the substrate surface, the mask material gives rise to shades, causing the patterns to be asymmetric and resulting in variation in the properties of the element devices thus produced. Moreover, difficulties arise in estimating the area ion implantated from the mask size. The smaller the pattern becomes for high integration, the more the drawbacks increase. Since the respective positions on the substrate have different separations from the ion source, said positions are electrically charged to different degrees by an ion beam-accelerating electric field, thus causing ions to be implanted with different densities. Consequently variations appear in the properties of the element devices formed on the substrate. Moreover, some ion-implanting devices do not allow the substrate rotation angle to be freely defined. When, therefore, such an ion-implanting device is used, it is impossible to produce highly reliable semiconductor devices. Therefore, the rotation angle of the substrate plane has to be determined for each substrate, requiring a great deal of work.
The above-mentioned difficulties particularly arise in a semiconductor device having an extremely fine circuit arrangement, for example, a high speed digital IC or a high frequency analog IC fabricated by forming an MESFET on a GaAs single crystal substrate.